TEDGPL=0, TCK=others, TMOD=000
AGT Mode Register 1
| TMOD | Operating mode 0 (others): settings are prohibited 0 (000): Timer mode 1 (001): Pulse output mode 2 (010): Event counter mode 3 (011): Pulse width measurement mode 4 (100): Pulse period measurement mode. |
| TEDGPL | Edge polarity 0 (0): Single-edge 1 (1): Both-edge. |
| TCK | Count source 0 (000): PCLKB 0 (others): settings are prohibited. 1 (001): PCLKB/8 3 (011): PCLKB/2 4 (100): Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register 5 (101): Underflow event signal from AGT0*6 6 (110): Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register. |
| Reserved | This bit is read as 0. The write value should be 0. |